A. Field of the Invention
The present invention relates to semiconductor devices.
B. Description of the Related Art
In the field of electric power converters using a semiconductor device, matrix converters have been known to the persons skilled in the art as direct converter circuits which conduct an alternating current to alternating current conversion (hereinafter referred to an “AC/AC conversion”), an alternating current to direct current conversion (hereinafter referred to an “AC/DC conversion”) and a direct current to alternating current conversion (hereinafter referred to as a “DC/AC conversion”).
The matrix converter includes AC switches. Since an AC voltage is applied to the AC switches, it is required for the AC switches to exhibit withstand voltages in the forward and reverse directions. In other words, the AC switches are required to exhibit a forward withstand voltage and a reverse withstand voltage. From the view points of reducing the size, weight and costs of the matrix converter and improving the conversion efficiency and response speed thereof, bidirectional switching apparatuses have been attracting much attention. As one of the bidirectional switching apparatuses, a switch including two reverse blocking insulated gate bipolar transistors (hereinafter referred to as “reverse blocking IGBTs”) connected in parallel to each other has been known to the persons skilled in the art.
FIG. 10 is the cross sectional view of a conventional reverse blocking IGBT. In the following descriptions and the accompanied drawings, electrons or holes are the majority carries in the layers and regions prefixed with “n-type” or “p-type”.
Referring now to FIG. 10, separation section 210 is formed in the edge area of an n-type semiconductor substrate in the reverse blocking IGBT for separating the crystal defects, caused in the side plane of the semiconductor substrate by dicing the semiconductor substrate into chips, from active region 100. In active region 100, a vertical IGBT, including n-type drift region 1, p-type channel region 2, n-type emitter region 3, and p-type collector region 10, is formed. In separation section 210, separation region 211 is formed through the semiconductor substrate from the substrate front surface to the substrate back surface such that separation region 211 covers the substrate side plane. Separation region 211 is connected to collector region 10 formed on the active region 100 back surface.
By disposing separation region 211 as described above, a depletion layer expands along separation region 211 from collector region 10 on the substrate back surface, when a reverse voltage is applied. Therefore, the depletion layer is prevented from reaching the substrate side plane and a leakage current is prevented from causing in the reverse blocking IGBT as shown in FIG. 10. Therefore, it is possible to provide the reverse blocking IGBT with a reverse withstand voltage. Between separation region 211 and active region 100, breakdown-withstanding junction edge-termination region (hereinafter referred to simply as “breakdown withstanding region”) 200 is formed. Breakdown withstanding region 200 relaxes the electric field on the pn-junction constituting the semiconductor device and realizes the desired withstand voltages.
FIG. 11 is a cross sectional view showing active region 100 in the semiconductor device in detail.
In active region 100, p-type channel region 2 is formed selectively in the surface portion on the front side of drift region 1 constituting an n-type semiconductor substrate. In the channel region 2 surface portion, n-type emitter region 3 and p-type body region 4 are formed selectively. Above drift region 1, gate electrode 7 is formed with gate insulator film 6 interposed between drift region 1 and gate electrode 7. On gate electrode 7, interlayer insulator film 8 is formed. Emitter electrode 9 is formed such that emitter electrode 9 is in contact with emitter region 3 and body region 4. Emitter electrode 9 is insulated from gate electrode 7 by interlayer insulator film 8. On the back surface side of drift region 1, p-type collector region 10 and collector electrode 11 are formed.
FIG. 12 is a cross sectional view showing breakdown-withstanding junction edge-termination region 200 in the semiconductor device in detail.
In breakdown-withstanding junction edge-termination region (hereinafter referred to simply as “breakdown withstanding region”) 200, a plurality of field limiting rings (hereinafter referred to as “FLRs”) 201, which are floating p-type regions, is formed in the surface portion on the drift region 1 front side. The drift region 1 front surface, under which FLR 201 is not formed, is covered with interlayer insulator film 8. On interlayer insulator film 8, field plate (hereinafter referred to as “FP”) 202, that is a floating electrically conductive film, is formed. FP 202 is in contact with and connected electrically to FLR 201. In the substrate edge area, field plate 212 having the potential the same with the separation region 211 potential (hereinafter referred to as “equipotential FP 212”) is formed on interlayer insulator film 8. Equipotential FP 211 is in contact with and connected electrically to separation region 212.
Breakdown withstanding region 200 includes a region (hereinafter referred to as a “forward breakdown withstanding region”) that improves mainly the forward withstand voltage, when a voltage is applied in the forward direction, and a region (hereinafter referred to as a “reverse breakdown withstanding region”) that improves mainly the reverse withstand voltage, when a voltage is applied in the reverse direction. Although not illustrated in FIG. 12, the forward breakdown withstanding region is formed on the active region 100 side in breakdown withstanding region 200. The reverse breakdown withstanding region is formed on the edge area side in breakdown withstanding region 200. In addition to the forward and reverse breakdown withstanding regions, a plurality of FLRs 201 described above and a plurality of FPs 202 described above are formed.
FIG. 13 is a cross sectional view showing the forward breakdown withstanding region in the semiconductor device in detail.
In breakdown withstanding region 200, p-type channel stopper region 231 is formed between forward breakdown withstanding region 220 and reverse breakdown withstanding region 240. Field plate 232 (hereinafter referred to as middle FP 232”) is connected electrically to channel stopper region 231. Forward breakdown withstanding region 220 is formed between active region 100 and middle FP 232. In forward breakdown withstanding region 220, field plate 222 (hereinafter referred to as “inner FP 222”) connected electrically to field limiting ring 221 (hereinafter referred to as “inner FLR 221”) is formed such that inner FP 222 projects toward the edge area of breakdown withstanding region 200.
FIG. 14 is a cross sectional view showing the reverse breakdown withstanding region in the semiconductor device in detail.
Reverse breakdown withstanding region 240 is formed from middle FP 232 to the edge area side of breakdown withstanding region 200. In reverse breakdown withstanding region 240, field plate 242 (hereinafter referred to as “outer FP 242”) connected electrically to field limiting ring 241 (hereinafter referred to as “outer FLR 241”) is formed such that outer FP 242 projects toward active region 100.
The following Patent Document 1 proposes a planar-type semiconductor device exhibiting a high withstand voltage as the reverse blocking IGBT described above. The proposed semiconductor device includes a semiconductor substrate of a first conductivity type; a separation diffusion region of a second conductivity type extended from the first major surface of the semiconductor substrate to the second major surface thereof; a base region of the second conductivity type including a planar junction and formed on the first major surface side of the semiconductor substrate surrounded by the separation diffusion regions; a junction edge-termination structure formed between the base region and the separation diffusion region; and a collector layer of the second conductivity type formed on the second major surface side of the semiconductor substrate and connected to the separation diffusion region. In the proposed semiconductor device, the junction edge-termination structure includes a ring-shaped floating guard ring of the second conductivity type formed in the peripheral surface portion around the base region with a spacing left between the adjacent floating guard rings; a field insulator film formed on the substrate surface between the separation diffusion region and the guard ring; a field insulator film formed on the substrate surface between the guard rings; a field insulator film formed on the substrate surface between the guard ring and the base region; an electrically conductive field plate in electrical contact with the separation diffusion region; an electrically conductive field plate in electrical contact with the guard ring; and an electrically conductive field plate in electrical contact with the base region. The electrically conductive field plate projects outward at least on the innermost field insulator film and the adjacent field insulator film. The electrically conductive field plate projects inward least on the outermost field insulator film and the adjacent field insulator film.
The following Patent Document 2 proposes another reverse blocking semiconductor device. The reverse blocking semiconductor device proposed in the following Patent Document 2 includes a base region of a second conductivity type formed selectively in the surface portion of a drift layer of a first conductivity type; an emitter region of the first conductivity type formed selectively in the surface portion of the base region; a MOS gate structure including a gate insulator film coated on the base region surface between the drift layer and the emitter region and a gate electrode coated above the base region with the gate insulator film interposed between the gate electrode and the base region; an emitter electrode in contact with the emitter region and the base region; a separation region of the second conductivity type formed such that the separation region is surrounding the MOS gate structure via the drift layer and connecting the front and back surfaces of the drift layer; a collector layer of the second conductivity type formed on the back surface of the drift layer and connected to the separation region exposed to the back surface of the drift layer; and a collector electrode in contact with the collector layer. The reverse blocking semiconductor device further includes a ring-shaped field limiting layer of the second conductivity type in the drift layer between the emitter electrode and the separation region; a ring-shaped field limiting electrode of a floating potential in contact with the field limiting layer; a plurality of the field limiting electrodes on the emitter electrode side having a large extended portion extended outward; and a plurality of the field limiting electrodes on the separation region side having a large extended portion extended inward.
The extensive and intensive investigations conducted by the present inventors have revealed the following points.
If outer FPs 242 connected electrically at least to outermost outer FLR 241 and adjacent outer FLR 241 in the reverse breakdown withstanding region are projected toward active region 100 as described in Japanese Unexamined Patent Application Publication No. 2005-101254 (hereinafter “Patent Document 1”) and Japanese Unexamined Patent Application Publication No. 2005-252212 (hereinafter “Patent Document 2), the depletion layer extending from separation region 211 at a reverse voltage application will extend easily toward active region 100. Therefore, electric field localization will be caused in channel stopper region 231 that suppresses the depletion layer expansion and electric field strength rise may be caused therein. To obviate this problem, it is necessary to elongate the spacing between separation region 211 and channel stopper region 231 (the reverse breakdown withstanding region 240 width) as long as the length, for which the depletion layer is liable to additional extension. In other words, the breakdown withstanding region 200 length between active region 100 and separation region 211 (hereinafter referred to as the “breakdown withstanding region 200 width”) will be elongated and the reverse blocking IGBT will be enlarged in the total size thereof. Therefore, it is difficult to reduce the reverse blocking IGBT area.
Generally, the upper limit of the current capability (the withstand voltages) is improved by disposing a breakdown-withstanding junction edge-termination region as compared with the elimination of the breakdown-withstanding junction edge-termination region. However, since the main current does not flow through the breakdown-withstanding junction edge-termination region, the current capability of the semiconductor device itself is not improved. Therefore, for reducing the reverse blocking IGBT area, it is preferable for breakdown withstanding region 200 to be small as much as possible in the size thereof.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a semiconductor device that facilitates reducing the reverse blocking IGBT area. It would be further desirable to provide a semiconductor device that facilitates improving the withstand voltages thereof.